1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly to a BICMOS level shifter for changing an emitter coupled logic(ECL) signal to a CMOS logic signal or a bipolar logic signal, and a data output buffer using the same.
2. Description of the Related Arts
As semiconductor integrated circuits become more highly integrated and of higher speed, signal noise problems increase. One of the significant signal noises in semiconductor integrated circuits is the noise generated from the data output driver of the data output buffer when read-out data from a predetermined memory cell is supplied off-chip from the data output buffer via an I/O line sense amplifier. The reason for this noise is that data output driver transistors buff the internal and external impedance of the chip and have a considerably wide channel width as compared to the other components in the chip in order to allow for high speed data access operations when a predetermined output operation (namely, at the swing operation from a "high" level to a "low" level or from the "low" level to the "high" level) starts, a large amount of current flows, which generates excessive consumption current. Particularly, ground noise is a problem since it gets applied to circuits in which the ground voltage is supplied to the source voltage. This is also true for Vcc noise.
As compared to the MOS transistor, the bipolar transistor can operate at a higher speed and have greater drive capability. Therefore, bipolar transistors are preferred components for output circuitry.
To solve the above problems, a predetermined current control circuit is provided in the pull-up or pull-down portions of the data output driver of the data output buffer. U.S. Pat. No. 4,636,665 teaches one example of this particular technique in which bipolar transistors are used in order to achieve the high speed operation and high drive capability. This technique discloses an inverter-type BICMOS level shifter, that is, a BICMOS data output buffer, which uses respective NPN-type bipolar transistors at the pull-up and pull-down portions and MOS transistors for controlling the NPN-type bipolar transistors. The above-described application has a feature which makes it possible to secure high drive capability during a data output operation and to perform the current transfer operation at a high speed by utilizing the feature of the bipolar transistors. However, due to the low drive capability of the MOS transistor driving the bipolar transistor, the high speed operation of the BICMOS data output buffer is limited. That is, the time required in driving the bipolar transistor of the data output driver is limited by the low drive capability of the MOS transistor. In this case, if the MOS transistor controlling the bipolar transistor is enlarged to improve the high speed operation and the drive capability, there may occur a problem that the amount of direct current is increased, and power consumption is thereby undesirably increased.
In order to overcome the above problem, the present inventor proposed an improved technique in Korean patent No. 92-9671 (entitled "BICMOS LEVEL SHIFTER"). This improved technique provides an input circuit which is constructed in the form of a differential amplifier having MOS transistors and a data output driver which uses a bipolar transistor. The data output driver further comprises a pull-down portion including a MOS transistor, thereby solving the problem of instability of the output signal by the inter-switching operation of the pull-down bipolar transistors as well as enhancing drive capability and high speed operation. However, because it is impossible to control the unstable input of the control signals A and B supplied to the input circuit of the level shifter, a direct current is continuously generated and results in a large power consumption. In addition, the speed of the data output operation is lowered by the loading capacitance formed in the data output driver.